Build FPGA and ASIC designs that meet timing.
What it does
Guides development of modular, verified FPGA and ASIC designs with attention to timing and hardware efficiency.
When to use it
Use when developing, verifying, or optimizing SystemVerilog designs for FPGA or ASIC hardware.
How to use it
It changes how the agent develops SystemVerilog project code by emphasizing reusable modules, clear interfaces, and consistent coding conventions.
What you provide
- An existing project
Latest review
What you need · 0
No setup requirements listed.
Access · 0
No additional actions listed.